(1) Field of the invention
The present invention relates to a structure of a dynamic type memory applicable to a video memory device and particularly to the structure of a dynamic type memory in which data input/output to and from a memory cell array is carried out via a register. The register converts input or output signals from serial-to-parallel form or parallel-to-serial form.
(2) Description of the prior art
FIG. 1 shows a conventional video memory.
In FIG. 1, numeral 1 denotes each memory cell, numeral 2 denotes a memory cell array (64 Kilobits or 64 KB) constituted by a plurality of the memory cells, numeral 3 denotes a sensing amplifier, numeral 4 denotes a row decoder, and numeral 5 denotes a register for converting a video signal having 256 bits for each horizontal period (H) read from the memory cell array 2 in a bit-parallel form into a bit-serial form.
The video memory shown in FIG. 1 transfers, for example, a 256-bit signal (read via a single word line selected by means of the row decoder 4) to the register 5, which register has a number of bits equal to the number of bit lines, in bit-parallel form, the register 5 outputting the 256-bit signal to an external device from the video memory in the bit-serial form. A high-speed reading of such a serial data is carried out by repetitions of switching the selected one of the word lines. In addition, such a video memory of a dynamic memory cell type is commonly used since it is superior in its high-speed processing capability, high-density integration, and reduced power consumption.
In a case where the video memory shown in FIG. 1 is constituted by the dynamic type memory described above, a holding capability of holding information stored in each memory cell 1 for a period of time more than a constant duration is necessarily required. As a large storage capacity of the memory is advanced along with a higher quality of video images, a higher holding capability is required for each memory cell. It becomes difficult to meet such a higher demand.
A more detailed description of its difficulty in meeting the demand will be made as follows.
That is to say, the video memory shown in FIG. 1 needs to continue to hold a stored signal for a time duration from a time when one of the word lines to access the stored signal in the corresponding memory cell is selected up to a next time when the same word line is selected. The selection of the word lines is carried out in such an order that at first the first word line, secondly the second word line, and finally the 256th word line and in this order one reading of the memory signals is completed. Upon completion of the reading of the stored signal from the 256th word line, the reading is returned to the first word line. The time duration required to hold the stored signal is a product of a cycle time of the serial data, the number of bit lines, and the number of the word lines. Specifically, suppose that the cycle time is 70 nanoseconds (nS) in the case of 64 KB video memory. The time duration described above is 4.6 milliseconds (mS). In the case of 256 KB video memory the time duration amounts to 18 mS. Therefore, it is not easy for all memory cells to hold the stored signals for such a long time duration. This provides the cause of reducing a yield of the video memory products, and a major problem arises due to the strict demand for the memory cells to have the high information holding capabilities.
On the other hand, in the conventional video memory shown in FIG. 1, the capacity of the register 5 which converts the video signal in the bit-parallel form into the bit-serial form needs to be, for example, 256 bits per one horizontal line (1H). Therefore, an occupying area of the register 5 becomes very large so that an area of one semiconductor chip for the dynamic type memory needs accordingly to be large.
Furthermore, the following problem occurs in the conventional video memory shown in FIG. 2.
In FIG. 2, numeral 6 denotes a portion of the video memory, numeral 2 denotes the memory cell array comprising a multiple number of storage elements. Numeral 5i denotes an input shift register for converting the input video signal inputted in the serial form into the parallel signal for one horizontal line (H), the video signal in the parallel form stored in the shift register 5.sub.i being stored in the memory cell array 2. Numeral 5.sub.o denotes the shift register outputting the bit-serial signals with the video signal read from the memory cell array 2 in the bit-parallel mode stored.
Numeral 4 denotes a row decoder, numeral 7 denotes a control circuit which latches external control signals in response to a reference clock pulse externally provided and controls the memory cell array 2 in response to the respective control signals. The control circuit 7 includes a latch portion 8 which latches the control signals and a control portion 9 controlling the memory cell array 2.
Numeral 10 denotes a control unit for controlling the memory 6 externally. Control signals produced on the basis of the reference clock pulse and also the reference clock are supplied to the memory portion 6. Numeral 11 denotes a crystal oscillator, numeral 12 denotes an original oscillator for generating an original oscillating pulse using the crystal oscillator 11. Numeral 13 denotes a clock pulse generator for dividing and shaping the output signal from the original oscillator 12 to generate a reference clock pulse (3.58 (subcarriers).times.4 MHz). Symbols LG 1 to LG n denote logic circuits for providing desired various kinds of control signals from the above-described reference clock pulse. Symbols DL 1 to DL n denote delay circuits for delaying the control signals produced by the logic circuits LG 1 to LG n by a predetermined time. The respective control signals are delayed by means of the delay circuits DL and inputted into the memory portion 6.
The reasons that the control signals are delayed by means of the delay circuits and applied to the memory 6 will be described below.
That is to say, each control signal needs to rise or fall at a timing prescribed according to a set-up time or hold time determined according to characteristics and capabilities of the control circuit 7 of the memory portion 6 with respect to the falling edge (or rising edge) of the reference clock pulse.
For example, to latch the control signals, as shown in FIG. 3, each control signal needs to rise (or fall) prior to, e.g., the rising edge of the reference clock pulse by at least more than set-up time and each control signal needs to be held in the rising state (or falling state) during the hold time after the reference clock pulse rises. However, the control signal derived from each logic circuit LG is synchronized with the rising edge (or falling edge) of the reference clock pulse. The control signal cannot rise (or fall) prior to the rising edge of the rising (or falling) of the reference clock by the set-up time and holds its rising state (or falling state) until the passage of time of the hold time after the reference clock pulse rises (or falls). This is called the requirements of the set-up time and hold time, which must be satisfied. In order to meet the requirements of the set-up time and hold time, an appropriate delay needs to be provided for each control signal. The delay circuits DL 1, DL 2, . . . DL n are installed to provide the delays.
Another major problem arises in the conventional video memory.
The delay time provided for the control signals by means of the above-described delay circuits DL 1, DL 2, . . . , DL n is not dependent on the performance of the control circuit 7 but dependent on the performance of the memory 6. Therefore, the design of the control circuit 7 needs to follow the selection of the memory.
A video equipment manufacturer needs to manufacture logic circuits and/or delay circuits after the selection of one of the video memories manufactured by a semiconductor manufacturer. Therefore, an interval of time from the time when a new product is developed to a time when the new product is sold becomes very long so that it becomes difficult to adapt such a recent trend that a life cycle of a new product becomes shortened.